# SPDX-License-Identifier: GPL-2.0+
# Copyright 2022-2023 NXP

if NXP_S32CC

config DEFAULT_DEVICE_TREE
	default "s32cc"

config BUILD_TARGET
	default "u-boot-s32.cfgout"

config SYS_TEXT_BASE
	default 0xffaa0000

config SYS_LOAD_ADDR
	default 0x80000000

config SYS_DATA_BASE
	hex "Data Base"
	default 0xffa00000
	help
	  U-Boot data base address in DDR.

config S32CC_MAX_DTB_SIZE
	hex "Max size reserved for device tree in image layout"
	default 0x8000

config SYS_MALLOC_F_LEN
	default 0x8000

config S32CC_QSPI_FREQ
	int "QSPI frequency setting (MHz) used in order to set BootROM's clock"
	default 200

config BOARD_NFS_BOOT_INTERFACE
	string "Board NFS Boot Interface"
	default "br0" if TARGET_S32G274ABLUEBOX3
	default "eth0"

config S32CC_HWCONFIG
	string "S32CC HWConfig definition"
	depends on PHY_S32CC_SERDES
	default "serdes0:mode=xpcs0&xpcs1,clock=ext,fmhz=125;xpcs0_0:speed=2G5;xpcs0_1:speed=2G5;serdes1:mode=xpcs0&xpcs1,clock=ext,fmhz=125;xpcs1_0:speed=2G5;xpcs1_1:speed=2G5" if (!PCI_S32CC && FSL_PFENG)
	default "serdes0:mode=pcie,clock=ext;pcie0:mode=rc;serdes1:mode=pcie,clock=int;pcie1:mode=ep" if (PCI_S32CC && !FSL_PFENG)
	default "serdes0:mode=pcie,clock=ext;pcie0:mode=rc;serdes1:mode=xpcs0&xpcs1,clock=ext,fmhz=125;xpcs1_0:speed=2G5" if (PCI_S32CC && FSL_PFENG)

	help
	  The configuration for the SerDes modules, stored in
	  the variable 'hwconfig'.
	  It configures generic attributes for 'serdesX', such as 'mode' (see below),
	  the clock type (internal or external),
	  clock frequency 'fmhz' (100 or 125, SGMII only modes), 'pcieX' mode
	  ('rc' or 'ep') and the 'xpcsX_Y' interfaces for any of the two lanes.
	  In the atributes presented above and below, 'X' (0 or 1) is the index
	  of the SerDes module and 'Y' (0 or 1) is the index of the XPCS interface.
	  SerDes 'mode' attribute can be 'pcie' (PCIe only mode), 'pcie&xpcsY' (PCIe
	  and SGMII combo mode), 'xpcs0&xpcs1' (SGMII only mode).
	  For the combo modes 'pcie&xpcsY', lane0 is PCIe and lane1
	  is connected to a GMAC or PFE MAC depending on 'Y' and 'fmhz' (which
	  match a certain SerDes configuration from the SerDes manual).
	  PCIe always works at 100MHz, therefore 'fmhz' is only for SGMII only mode.
	  Config 'xpcsX_Y' is used to specifically configure each of the two SGMII
	  PHYs, by setting the 'speed' (10M, 100M, 1G and 2G5).
	  S32G2 and S32G3 have 1 GMAC running at 1Gbps and 3 PFE MACs, running at
		10Mbps - 2.5Gbps speeds.
	  S32R45 has two GMACs, GMAC0 running at 1Gbps and GMAC1 running at 2.5Gbps.

config S32CC_HWCONFIG_LEGACY
	bool "Legacy S32CC HWConfig definition"
	default y
	depends on PHY_S32CC_SERDES
	help
	  Support for old format for variable HWCONFIG. Each SerDes
	  is identified by the string 'pcieX' and is configured by a list of
	  attributes such as 'mode' (rc, ep, sgmii) and the clock type
	  (internal or external).
	  It is also possible to configure combo modes, either 'ep&sgmii' or
	  'rc&sgmii', with these configurations lane0 is PCIe and lane1
	  is connected to GMAC of PFE mac depending on 'xpcs_mode'.
	  'sgmii' mode uses additional config options 'fmhz' and 'xpcs_mode'.
	  Config 'xpcs_mode' is used to specifically configure each line in
	  SGMII mode. The following are valid options: '2G5', 'both', '0' and
	  '1'. Mode '2G5' uses lane0 in 2.5G mode and leaves lane1 disabled.
	  Mode 'both' configures both lanes for 1G operation so 2 macs can
	  be connected. Mode '0' is used to configure only XPCS0, this can be
	  used in 'sgmii' mode (one lane emac 1G other lane disabled) or
	  in 'rc&sgmii'/'ep&sgmii' (one lane PCIeX1, the other lane SGMII 1G).
	  Same configuration is used for '1', which corresponds to XPCS1.
	  Config 'fmhz' specifies frequency used as reference. In case of
	  2.5G mode it is required to set this 125, if used in SGMII/PCIe
	  combo mode 'fmhz' has to be 100 (PCIe ignores this and always
	  uses 100). In case the SerDes is configured as SGMII and not in
	  2.5G mode either 100 or 125 can be used in 'fmhz'.
	  Available 'xpcs_mode' are dependent on platform:
		s32g274a - supports '0','1','both' and '2G5'
		s32r45   - supports '0' and '2G5'
	  By default, legacy HWCONFIG was:
	  "pcie0:mode=rc,clock=ext;pcie1:mode=sgmii,clock=ext,fmhz=125,xpcs_mode=2G5"
	  This has lots of limitations, and has been redesigned.

config S32CC_CONFIG_FILE
	string
	default "arch/arm/mach-s32/s32-cc/s32cc.cfg"

config TARGET_TYPE_S32CC_EMULATOR
	bool
	default n

config LMB_MAX_REGIONS
	default 16

if TARGET_TYPE_S32CC_EMULATOR
config BAUDRATE
	default 7812500
endif

config ENV_OFFSET
	default 0x1e0000

config SF_DEFAULT_BUS
	default 6

config SF_DEFAULT_CS
	default 0

if SD_BOOT
config ENV_IS_IN_MMC
	default y

config ENV_SIZE
	default 0x2000
endif

if QSPI_BOOT
config ENV_IS_IN_SPI_FLASH
	default y

config ENV_SIZE
	default 0x10000

config ERR051257_WORKAROUND
	bool "ERR051257 erratum workaround"
	default y
	help
	  Enable workaround for ERR051257 erratum.
	  The QSPI boot flow will hang if the QSPI memory will rise any ECC
	  error interrupt. As a software solution for this issue, the pins
	  QSPI_INTA_b and QSPI_INTB_b are configured as GPIO from DCD and the
	  images(QSPI parameters for BootROM, DCD, HSE FW, etc) have an unused
	  space of 1K between them.
endif

config XEN_SUPPORT
	bool "Enable Xen EL2 Booting and set environment variables in order to boot directly into Xen Hypervisor"
	default n
	help
	  Skip the enablement of CONFIG_ARMV8_SWITCH_TO_EL1 and set Xen Image,
	  fdts load addresses and U-Boot environment variables in order for U-Boot
	  to directly load the Xen Image which will use a given Kernel Image as
	  Dom0.

endif

source "arch/arm/mach-s32/s32g2/Kconfig"
source "arch/arm/mach-s32/s32g3/Kconfig"
source "arch/arm/mach-s32/s32r45/Kconfig"
source "board/nxp/s32-cc/Kconfig"
